Over the last few decades, the electronics industry has undergone a revolution through the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, complimentary MOS (CMOS) transistors, bipolar transistors, bipolar CMOS (BiCMOS) transistors, etc.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode which modulates current between the source and drain regions. In bipolar transistors, an active device generally includes a base, a collector, and an emitter.
Semiconductor devices, like the ones mentioned above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon substrate, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral and vertical dimensions of the device structure.
One important step in the formation of semiconductors is the process of electrically isolating adjacent active devices. One known technique for isolating active devices on a semiconductor substrate is LOCOS (LOCal Oxidation of Silicon) isolation. LOCOS isolation generally involves the formation of a recessed or semi-recessed oxide 20 in the nonactive (or field) areas 22 of a substrate 24 which separate the active devices 26, as illustrated in FIG. 1A.
In one particular LOCOS process, a thin silicon dioxide layer, often referred to as a pad oxide layer is grown on the surface of a semiconductor substrate. A relatively thick layer of silicon nitride is then deposited over the pad oxide layer. Using a mask and etch process, the pad oxide/nitride layers are then selectively removed to define active regions (generally those regions masked by the pad oxide/nitride layers) and field regions (generally those regions over which the pad oxide/nitride layers have been removed). The nitride layer acts as a mask during subsequent oxide growth. An oxide, typically referred to as a field oxide, is thermally grown in the field regions to a thickness ranging from 0.3 to 1.0 .mu.m to electrically isolate the active regions. The pad oxide layer and nitride masking layer are then removed to expose the active regions of the substrate.
The structure resulting from LOCOS isolation techniques is typically associated with a number of limitations. One limitation in particular is the poor planarity of the resultant surface topography. This limits the maximum resolution of photolithography steps and serves to further impede scaling down of semiconductor devices. A second major limitation is the encroachment of the active area by the field oxide.
One alternative to LOCOS isolation is trench isolation. Trench isolation generally involves etching shallow trenches 28 in field regions 22 of the substrates 24 and refilling the trenches with a deposited silicon dioxide layer 30, which is etched back to yield a relatively planar surface, as depicted in FIG. 1B. Trench isolation generally improves the planarity of the surface topography of the device, as well as the junction edge capacitance. In general, trench isolation also provides better isolation and latch-up performance. However, current trench isolation techniques gives rise to other problems. For example, deleterious voids can form in the deposited silicon dioxide. These voids become more pronounced as the trenches become narrower.
Furthermore, achieving improved planarity using trench isolation is often difficult and costly. For example, the deposited silicon dioxide layer used to fill the trenches is typically conformally deposited using a technique such as chemical vapor deposition (CVD). This results in divots in the deposited silicon dioxide layer associated with the trenches. These divots make the planarization of the device surface difficult. The methods used to alleviate these divots generally involve further processing steps. Each of these steps adds to the overall cost and time to manufacture a semiconductor device. A more detailed discussion of the LOCOS and trench isolation techniques as well as the advantages and disadvantages resulting therefrom can be found in S. Wolf, Silicon Processing For The VLSI Era, Vol. 2: Processing Integration, Chap. 2, pp. 12-66, 1990.